PIC16F639-E/SO【PDF 19/74 页】IC MCU FLASH 2KX14 20SOIC

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3878

15页 16页 17页 18页 [19页]20页 21页 22页 23页

Micrel, Inc.

KSZ8841-PMQL

October 2007

M9999-100407-1.5

The following table shows the RDES1 register bit fields.

Bit

Description

31 - 26

Reserved

RER Receive End of Ring

When set, indicates that the descriptor list reached its final descriptor. The KSZ8841-PMQL

returns to the base address of the list, thus creating a descriptor ring.

24 - 12

Reserved

10 - 0

RBS Receive Buffer Size

Indicates the size, in bytes, of the receive data buffer. If the field is 0, the KSZ8841-PMQL

ignores this buffer and moves to the next descriptor.

The buffer size must be a multiple of 4.

The following table shows the RDES2 register bit fields.

Bit

Description

31 - 0

Buffer Address

Indicates the physical memory address of the buffer.

The buffer address must be Word aligned.

The following table shows the RDES3 register bit fields.

Bit

Description

31 - 0

Next Descriptor Address

Indicates the physical memory address of the next descriptor in the descriptor ring.

The buffer address must be Word aligned.

Transmit Descriptors (TDES0-TDES3)

Transmit descriptors must be Word aligned. Each descriptor provides one frame buffer, one byte count field, and

control and status bits.

The following table shows the TDES0 register bit fields.

Bit

Description

OWN Own Bit

When set, indicates that the descriptor is owned by the KSZ8841-PMQL. When cleared,

indicates that the descriptor is owned by the host. The KSZ8841-PMQL clears this bit either

when it completes the frame transmission or when the buffer allocated in the descriptor is

empty.

The ownership bit of the first descriptor of the frame should be set after all subsequent

descriptors belonging to the same frame have been set. This avoids a possible race

condition between the KSZ8841-PMQL fetching a descriptor and the driver setting an

ownership bit.

30 - 0

Reserved

The following table shows the TDES1 register bit fields.

Bit

Description

IC Interrupt on Completion

When set, the KSZ8841-PMQL sets transmit interrupt after the present frame has been

transmitted. It is valid only when last segment is set.

FS First Segment

When set, indicates that the buffer contains the first segment of a frame.

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式